AMD Helion brings a CPU focus to AI racks
AMD introduced Helion on October 12 as an open rack blueprint for agentic AI. Its CPU configuration uses sixth generation EPYC processors for up to 32,768 cores, running agents while connecting to separate infrastructure for model inference.
For enterprises, a second design puts EPYC processors, Instinct MI350P GPUs and general computing in one rack. The blueprint allows air and liquid cooling.
Why agents need CPU capacity
The distinction matters because an agent has work to do between model responses. AMD’s EPYC 9006 documentation identifies retrieval and tool execution as CPU workloads. A system can therefore need more capacity to run tools and handle data even when the model serving those agents runs elsewhere.
That processor family uses Zen 6 and Zen 6c architectures, with up to 256 cores and 512 threads per processor. AMD distinguishes dense processors for parallel agent execution from higher frequency designs for latency sensitive orchestration and GPU host tasks. The relevant choice depends on where the application spends its time.
Core counts alone cannot establish useful agent throughput. AMD’s own footnotes describe estimates based on available threads as a proxy. Actual capacity depends on the workload, model, memory, software and system configuration. Buyers would need application measurements before translating a rack specification into a number of working agents.
What the GPU option adds
The MI350P specifications describe a CDNA4 accelerator with 128 compute units and 144 GB of HBM3E memory. Its memory bandwidth reaches a theoretical peak of 4 TB/s. These are specifications for an individual accelerator, so they should not be read as measurements of a complete agent application.
The card connects through PCIe 5.0 x16 and occupies two slots. AMD lists passive cooling and a maximum board power of 600 watts, configurable to 450 watts. That gives system designers concrete electrical and physical requirements to accommodate, even when they are using an existing server environment.
AMD’s architecture documentation adds an important qualification for sharing the GPU. The MI350P combines four compute dies with one input and output die. It supports up to four compute partitions, while its 144 GB uses a single memory partition. Dividing compute resources does not multiply the card’s memory capacity.
Availability remains a plan
AMD also describes a token router for directing model calls across frontier and open models. Detailed routing policies are not specified in the announcement.
The company plans to contribute the specification to the Open Compute Project. Partner rack configurations remain under development, with availability planned for November 2026. That timetable is AMD’s stated target rather than confirmation of delivered systems.
Our report on AMD’s 2027 supply plans covers the broader effort to coordinate wafer and memory capacity.
